1. Technical Field
This disclosure relates generally to test equipment and more specifically to compressed scan testing.
2. Description of the Related Art
Scan-based design-for-test (DFT) techniques are often used to facilitate circuit testing, e.g., to detect manufacturing defects. In scan-based design, circuitry (e.g., flip-flops or latches) in a device under test (DUT) is coupled to one or more scan chains which are used to gain access to internal nodes. Test patterns are shifted in via the scan chains, functional clock signals are pulsed to the circuitry during “capture” cycles, and results are shifted to output pins and compared to expected results.
Automatic test equipment is often used to test circuitry using scan-based techniques. Decreasing testing time and/or increasing test accuracy may decrease product costs and result in competitive advantages in various industries. However, scan-based techniques often involve long input patterns which may increase testing time and/or require a large number of input/output pins. Test compression techniques may be used in which a compressed input pattern is provided to a smaller number of input pins (than the number of scan chains), then decompressed and provided to internal scan chains. Outputs of the scan chains are then compacted and provided via a smaller number of output pins. Test compression may reduce testing times and the number of required input/output pins, especially for tests in which a relatively small number of scan cells need to take specific values. However, unknown design values (typically represented using an ‘X’) may cause difficulty in definitively determining the scan cell causing a particular failure, e.g., because the outputs of multiple scan chains may be XOR'd when compacted. This phenomenon is often referred to as “X-masking.”